Operating System Timer

The OST contains 3 independent timers. They count down from a user-set value and then auto-reload with that value. It has one 8 bit register and 4 registers (2 of 32 bit, one of 16 bit) per timer.

Of the 8 bit register, OST_TER, only the lower 3 bits are interesting. They enable or disable a timer: bit 0 for timer 0, etc. The other registers are:

• OST_TRDR: Reload value. This determines the time between two interrupts (if they are enabled).
• OST_TCND: The current value of the timer.
• OST_TCSR: Control settings: whether it should give an interrupt, whether it is or would currently giving an interrupt, and the divider value.
• OST_TCRB: Unknown.

Iris uses OST channel 0 as its source for timed interrupts, because the CPU counter does not run. Linux also uses it, but the documentation says they would also do this if the counter would work.

-- BasWijnen - 20 Jul 2009