TWiki> Epc700 Web>HardwareLayout>JzGPIO (23 Nov 2008, ArdVanBreemen)EditAttach
GPIO SYS WHAT COMMENT
000 KBD I Column 0
001 KBD I Column 1
002 KBD I Column 2
003 KBD I Column 3
004 KBD I Column 4
005 KBD I Column 5
006 KBD I Column 6
007 KBD I Column 7
008 ? ? According to source OR of GPIO0...7
009 LED O Ethernet Led
010 ? ? (CIM_PCLK)
011 ? ? (CIM_MCLK)
012 NE NE (replaced by chip mode)
013 KBD I TP_MOUSE_RIGHT
016 KBD I TP_MOUSE_LEFT
017 BAT I Something battery? Weird...
018 NE NE NE
019 NE NE NE
020 NE NE NE
021 MSC O MSC Power Enable
022 NE NE NE
023 JZSPEC   UART3_RTS
024 JZSPEC   UART1_RXD
025 JZSPEC   UART1_TXD
026 SND I headphonejack plug detection
027 LED O Capslock led
028 USB I USB_CLK 48Mhz clock input
029 USB O PPWR0 Power enable port 0
030 NE NE NE
031 NE NE NE
032 JZSPEC PS2_CLOCK  
033 JZSPEC PS2_DATA  
034 MSC IO MSC_DAT0
035 MSC IO MSC_DAT1
036 MSC IO MSC_DAT2
037 MSC IO MSC_DAT3
038 MSC IO MSC_CMD Msc command
039 MSC O MSC_CLK Msc clock output
040 LCD O LCD_D0
041 LCD O LCD_D1
042 LCD O LCD_D2
043 LCD O LCD_D3
044 LCD O LCD_D4
045 LCD O LCD_D5
046 LCD O LCD_D6
047 LCD O LCD_D7
048 LCD O LCD_D8
049 LCD O LCD_D9
050 LCD O LCD_D10
051 LCD O LCD_D11
052 LCD O LCD_D12
053 LCD O LCD_D13
054 LCD O LCD_D14
055 LCD O LCD_D15
056 LCD O LCD_VSYNC
057 LCD O LCD_HSYNC
058 LCD O LCD_PCLK
059 LCD O LCD_DE (DATA ENABLE)
060 LCD SPEN LCD_SPL
061 LCD SPCK LCD_CLS
062 LCD SPDA LCD_PS
063 LCD LCD_RET LCD_REV (used for reset)
064 MSC I MSC Card Detect
065 MCU IRQ mcu communications irq
066 MSC I MMSC Write Protect
067 JZSPEC   SCC1_CLK
068 SND I2S? _SYSCLK i2s system clock
069 SND I2S_PDN i2s connection
070 SND O I2S? _SDATAOUT
071 SND I I2S? _SDATAIN
072 JZSPEC   SSI_CLK output
073 JZSPEC   SSI_CE1 chip enable 1
074 JZSPEC   SSI_DT data transmit
075 JZSPEC   SSI_DR data receive
076 JZSPEC   SSI_CE2 chip enable 2
077 SND IO I2S? _BITCLK
078 SND IO I2S? _?
079 JZSPEC FRE Nand flash Read Enable
080 JZSPEC FWE Nand flash Write Enable
081 JZSPEC FRB Nand flash ready/busy
082 JZSPEC DCS1 SDRAM CS 1
083 JZSPEC CS1 SRAM CS 1
084 JZSPEC CS2 SRAM CS 2
085 JZSPEC CS3 SRAM CS 3
086 LED O Numlock led
087 JZSPEC CS5 SRAM CS 5
088 JZSPEC   PCMCIA_INPACK
089 JZSPEC   PCMCIA_BVD2
090 JZSPEC   PCMCIA_CE1
091 JZSPEC   PCMCIA_PSKTSEL
092 JZSPEC   PCMCIA_IOIS16
093 JZSPEC   PCMCIA_CE2
094 LCD PWM0 backlight
095 WIFI O USB port 4 Power Enable
096 KBD O Row 0
097 KBD O Row 1
098 KBD O Row 2
099 KBD O Row 4
100 KBD O Row 4
101 KBD O Row 5
102 KBD O Row 6
103 KBD O Row 7
104 KBD O Row 8
105 KBD O Row 9
106 KBD O Row 10
107 KBD O Row 11
108 KBD O Row 12
109 KBD O Row 13
110 KBD O Row 14
111 KBD O Row 15
112 ETH I MII_TX_EN TX enable
113 ETH I MII_RX_DV RX data valid
114 ETH I MII_RX_ER RX receive error
115 ETH I MII_COL collision
115 ETH I MII_COL collision
116 ETH I MII_CRS carrier sense
117 ETH O MII_TXD0 tx data 0
118 ETH O MII_TXD1 tx data 1
119 ETH O MII_TXD2 tx data 2
120 ETH O MII_TXD3 tx data 3
121 ETH O MII_RXD0 tx data 0
122 ETH O MII_RXD1 tx data 1
123 ETH O MII_RXD2 tx data 2
124 ETH O MII_RXD3 tx data 3
125 KBD O Row 16
126 UART O UART 0 TXD
127 UART I UART 0 RXD

ADDRESS SYS opmerking
50>>1 BAT MCU_DEV_ADDR

DEVICE PINS USED WHAT
UART2 111:RXD 125:TXD uart
SCC1 65:DATA smart card reader
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Topic revision: r5 - 23 Nov 2008 - 18:07:45 - ArdVanBreemen
 
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