Interrupt controller

The trendtac doesn't really use the interrupt system of the MIPS core. That provides 6 interrupt sources, one of which is automatically also the source for interrupts from the CPU timer and performance counters. However, since the XBurst doesn't have performance counters, and doesn't seem to have a running CPU timer, that doesn't matter much.

In the Jz4730, an interrupt controller is connected to the first hardware interrupt pin (IP2). All other pins are unconnected and will never generate interrupts. So instead of looking at the CAUSE register, the interrupt source must be looked for in the IPR register of the interrupt controller.

The controller has 5 registers:

• INTC_ISR: Unknown.
• INTC_IMR: Unknown; probably the current mask state for reading.
• INTC_IMSR: Set a bit here to mask an interrupt.
• INTC_IMCR: Set a bit here to unmask an interrupt.
• INTC_IPR: When read, it tells which interrupts are currently asserted. Writing a bit back resets the flag (unless it's still triggered).

There are 32 interrupt connections. The interrupt handler must check which interrupts are triggered, by reading IPR. It can then handle these interrupts. While a masked interrupt does not make the CPU jump to the interrupt handler, I expect (but didn't test) that it does set the bit in INTC_IPR. If that is indeed the case, and the masked interrupt is not to be handled, the interrupt handler must check the mask state before jumping to the handler, otherwise the handler may be called when some other interrupt is triggered.

The 32 connections are fixed to the devices. The list is in include/asm-mips/jz4730/regs.h. As can be seen there, pins 0, 5, 29 and 31 are not connected and will not generate interrupts.

Linux maps the GPIO pin interrupts and DMA interrupts to numbers above 32. However, this is a matter of software; all GPIO pin interrupts are reported by INTC as a single source per port, and the DMA controller also has a single interrupt pin on INTC.

-- BasWijnen - 20 Jul 2009