CPU

The system has an XBurst CPU, which uses the MIPS32 architecture. It has 32 TLB entries, no performance counters and no floating point coprocessor (CP1). It does report to have at least one watch register.

Contrary to the MIPS specification, it seems that the COUNT register of coprocessor 0 is not actually running. This means that the COMPARE register is also useless. The operating system timer (OST), external to the CPU (but internal to the Jz4730, I think) must be used for generating timed interrupts.

-- BasWijnen - 14 Jun 2009